I am a 3rd-year PhD student in the Department of Computer Science
at the University of Virginia, advised by Prof. Samira Khan.
My research interest lies in computer architecture and operating systmes, specifically in system and architectural for the imminent
Persistent Memory (PM) technologies.
Before that, I received my B.S degree from both Shanghai Jiaotong Unievrsity (SJTU) and the University of Michigan (UM) through the Dual-Degree Program.
Email: sihangliu
virginia.edu
Research
Rethinking Persistent Memory Systems
Advised by Prof. Samira Khan
The imminent persistent memory (PM) technologies, such as Intel and Micron’s 3D XPoint, SpinTransfer Torque RAM (STT-RAM), Phase-Change Memory (PCM), and Resistive Random-Access Memory (ReRAM) provide a unique opportunity to unify memory and storage, resulting in a new tier of memory referred to as persistent memory. Exploiting persistency in NVM systems require light-weight supports for crash consistency, security, data availability, etc. Conventionally, these system supports have been the responsibility of the OS and storage layer, however, we find out that the traditional system support significantly overshadows the benefits from PM’s low latency and byte-addressability. The goal of my research is to rethink these system supports in the context of PM systems, and determine the correct place and the right balance in cooperation between different system layers to implement the supports in a holistic and efficient manner.
Error-Restricted Approximate Computing
Advised by Prof. Samira Khan
Approximate computing trades precision for better performance and energy consumption. Adopting approximate memory is a common approach of approximate, that reduces the storage, energy and performance overhead in maintaining the correctness of memory cells. We observe that directly running error-resilient applications on approximate memory can cause extremely high errors in their output. As this uncontrolled error is the major cause of the skepticism and reluctance toward the adoption of approximate computing, the goal of this research is to restrict the error in approximate computing within a bound. Our key idea is based on a hardware-software co-design. We first restrict errors to less important bits in the data value. Then, we statically analyze the program’s data flow to obtain a bound of the maximum error in the output. Considering some mathematical operations, control flows and loops can cause a higher error than this bound, we finally perform a dynamic analysis during the program execution to handle these special cases.
Tail at Scale Effect in Network Protocols
Advised by Prof. Thomas Wenisch
Network latency is an important aspect to web services, such as online data analytics and web serach. Online data intensive (OLDI) applications typically scale up the computation platforms for better performance, where the overall latency depends on the slowest computation node. Therefore, the network tail latency is critical to the overall response time of OLDI applications. In this research, we destruct the latency of the common TCP, UDP and RDMA network protocols. Different from prior studies that analyze the latency due to extrinsic network parameters, such as network congestion, we rule out the external variations while focus on the latency from the operating system. Our experiments shows that the cause of the high tail latency is the TCP/UDP stack of the operating system.
Relaxed Persistency Model
Advised by Prof. Thomas Wenisch
The new persistent memory (PM) technologies blur storage and main memory. Programs can manage their recoverable data structures by directly access PM through a load-store interface, instead of using system calls to access the file system. Ensuring durability requires persistent data reach PM in a correct order. For example, when appending a new node to a linked list, the new node needs to become persistent in PM before the head pointer of the linked list gets updated. To allow programs maintain certain this ordering, Intel has provided new PM-specific instructions that enforces data writeback in the designated order. However, this solution ensures ordering and durability at the cost of performance, as the program execution (including accesses to volatile data) has to stall until writes become persistent. Our research proposes a delegated persist order that decouples the persistent operations from the volatile execution.
Conference Publications
Janus: Optimizing Memory and Storage Support for Non-Volatile Memory Systems
Sihang Liu, Korakit Seemakhupt, Gennady Pekhimenko, Aasheesh Kolli, and Samira Khan
The International Symposium on Computer Architecture (ISCA), 2019
[pdf][Lightning Talk][Slides]
PMTest: A Fast and Flexible Testing Framework for Persistent Memory Programs
Sihang Liu, Yizhou Wei, Jishen Zhao, Aasheesh Kolli, and Samira Khan
The International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2019
[pdf][Lightning Talk][Slides][Source Code]
Crash Consistency in Encrypted Non-volatile Main Memory Systems
Sihang Liu, Aasheesh Kolli, Jinglei Ren, and Samira Khan
IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018
[pdf][Lightning Talk][Slides]
Delegated Persist Ordering
Aasheesh Kolli, Jeff Rosen, Stephan Diestelhorst, Ali Saidi, Steven Pelley, Sihang Liu, Peter M. Chen, and Thomas F. Wenisch
Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016
[pdf]
Workshop Publications
Side Channel Attacks in Computation Offloading Systems with GPU Virtualization
Sihang Liu, Yizhou Wei, Jianfeng Chi, Faysal Hossain Shezan, and Yuan Tian
IEEE Workshop on the Internet of Safe Things (SafeThings), held in association with IEEE Symposium on Security and Privacy (Oakland), 2019
[pdf][Slides]
ARMOR: Towards Restricted Approximation with A Worst-Case Guarantee
Sihang Liu, Kevin Angstadt, Mike Ferdman, and Samira Khan
Workshop on Approximate Computing Across the Stack (WAX), held in association with the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2018
[pdf][Slides]
Deconstructing the Tail at Scale Effect Across Network Protocols
Akshitha Sriraman, Sihang Liu, Sinan Gunbay, Shan Su, and Thomas F. Wenisch
Workshop on Duplicating, Deconstructing, and Debunking (WDDD) held in association with the International Symposium on Computer Architecture (ISCA), 2016
[pdf]
Invited Talks
Janus: Optimizing Memory and Storage Support for Non-Volatile Memory Systems
At the 2019 International Symposium on Computer Architecture (ISCA) in Phoenix, AZ. [Slides]
Side Channel Attacks in Computation Offloading Systems with GPU Virtualization
At the 2019 IEEE Workshop on the Internet of Safe Things (SafeThings), held in association with IEEE Symposium on Security and Privacy (Oakland) in San Francisco, CA. [Slides]
PMTest: A Fast and Flexible Testing Framework for Persistent Memory Programs
At the 2019 International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) in Providence, RI. [Slides]
ARMOR: Towards Restricted Approximation with A Worst-Case Guarantee
At the 2018 Workshop on Approximate Computing Across the Stack (WAX), held in association with the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) in Williamsburg, VA. [Slides]